Embedded Code Generation for Efficient Reinitialization

Efficient automatic code generation for embedded systems

Developing a safety critical real-time application raises high challenge: “failure is not an option”. The code has to be readable, reliable and efficient. For doing so, VERILOG has developed an environment based on formal approach. This is the only way to be in a position to prove that the code is doing what it is supposed to do, always.

Faster Fuzzing: Reinitialization with Deep Neural Models

We improve the performance of the American Fuzzy Lop (AFL) fuzz testing framework by using Generative Adversarial Network (GAN) models to reinitialize he system with novel seed files. We assess performance based on the temporal rate at which we produce novel and unseen code paths. We compare this approach to seed file generation from a random draw of bytes observed in the training seed files. T...

Compact and Efficient Code Generation through Program Restructuring on Limited Memory Embedded System DSPs

Energy-Optimal Integrated VLIW Code Generation

Optimal integrated code generation is a challenge in terms of problem complexity, but it provides important feedback for the resource-efficient design of embedded systems and is a valuable tool for the assessment of fast heuristics for code generation. We present a method for energy optimal integrated code generation for generic VLIW processor architectures that allows to explore trade-offs bet...

Generating Multi-Threaded code from Polychronous Specifications

SIGNAL, Lustre, Esterel, and a few other synchronous programming language compilers accomplish automated sequential code generation from synchronous specifications. In generating sequential code, the concurrency expressed in the synchronous programs is sequentialized mostly because such embedded software was designed to run on single-core processors. With the widespread advent of multi-core pro...